The present invention relates to high input/output (I/O), high density, low cost electronic modules and, more particularly, to the high I/O, high density, low cost packaging of high performance, high density memory devices such as Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM) and having impedance-controlled buses for maintaining high electrical performance.
In data processing and network systems, it can always be certain that the demand in memory capacity will increase at a high rate. Such increase has in recent years taken on a new dimension; while memory demand increased, the space available for mounted memory devices has become increasingly restricted. The Electronic Industries Alliance (EIA) has set up a standard for the dimensions for rack-mountable equipment. Traditionally, a piece of rack-mountable equipment has a standard width of 19 inches and a height in increments of 1.75 inches. This is also known as xe2x80x9c1U.xe2x80x9d However, a trend has begun to reduce the height for the servers in a server rack to dimensions appreciably lower than 1U.
This equipment height restriction has also placed height restrictions on other components such as memory modules. The traditional SDRAM dual inline memory modules (DIMMs) are simply too tall to be able to be mounted vertically on the system board. Special sockets have been designed to allow DIMMs to be mounted either at an angle or even parallel to the system board. As the speed of memory devices increases to greater than 200 megahertz, for example, the electrical performance of such DIMM sockets is becoming inadequate.
One method being used today to solve the need to increase both memory capacity and density is to stack two, thin small outline package (TSOP) SDRAM devices on top of each other on a DIMM. An alternate approach is to stack two devices within a chip scale package (CSP). These stacking schemes, while increasing memory density, are not easily reworkable.
It is desirable to find a packaging solution that resolves both the capacity and the height issues. In addition, the solution must also be low in cost, readily manufacturable, upgradable with ample granularity, have improved electrical performance even at high frequencies, and have good reliability. Ample granularity allows the amount of memory on a given memory module to be increased or decreased in smaller increments (e.g., in increments of 256 megabytes, instead of one gigabyte).
It is therefore an object of the invention to provide a high capacity, high density, low profile SDRAM memory module for high performance memory devices.
It is another object of the invention to provide a high capacity, high density, low profile SDRAM memory module that is readily manufacturable and upgradable.
It is still another object of the invention to provide a high capacity, high density, low profile SDRAM memory module that provides improved electrical performance at high frequencies and good reliability.
The present invention is a family of specialized embodiments of the modules taught in the referenced copending U.S. patent applications. A memory module is desired with granularity, upgradability, and a capacity of two gigabytes using 256 MB SDRAM or DDR SDRAM memory devices in CSPs in a volume of just 4.54 inches by 2.83 inches by 0.39 inch.
Each module includes a substrate, having contact pads and memory devices on its surfaces, and impedance-controlled transmission line signal paths to support high speed operation. The substrates may be conventional printed circuit cards preferably with CSP packaged memory devices along with other components attached directly to both sides of the substrates.
The inclusion of spaced, multiple area array interconnections allows a row of memory devices to be symmetrically mounted on each side of each of the area array interconnections, thereby reducing the interconnect lengths and facilitating matching of interconnect lengths. The footprints for the interconnections between the substrates and to the system board are the same to reduce part number and reliability and qualification testing. Short area array interconnections, including ball grid array (BGA), pin grid array (PGA), and land grid array (LGA) options, or interchangeable alternative connectors, provide interconnections between modules and the rest of the system. The distance between the spaced multiple area array interconnections is preferably chosen to ensure that the solder joints in the BGA interconnection option are reliable.
Driver line terminators may be included on the substrates for maintaining high electrical performance. Thermal control structures may also be included to maintain the memory devices within a reliable range of operating temperatures.